(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly to a method for controlling the top oxide thickness on a polysilicon/silicon oxide/silicon nitride/silicon oxide/silicon substrate (SONOS) transistor while forming gate oxides of different thicknesses elsewhere on the substrate by a first and second embodiment. The method and structure are particularly suitable for integrating merged logic/analog integrated circuits with non-volatile memory devices.
(2) Description of the Prior Art
Merging semiconductor logic/analog devices with non-volatile memory devices is finding extensive use in the electronics industry. These embedded SONOS devices require FETs with different gate oxide thicknesses to optimize the FET performance. Typically non-volatile memory (SONOS) and peripheral input/output (I/O) devices require thicker gate oxides, while CMOS logic/analog devices require a thinner gate oxide for increased performance (switching speed). For example, SONOS memory and peripheral devices require thicker oxides of about 60 Angstroms or more and operate at a gate voltage of about 3.0 to 5.0 volts, while CMOS logic devices have gate oxides that are about 35 Angstroms or less and operate at lower gate voltages (V) of between about 1.8 V and 2.5 V to achieve higher switching speeds.
One conventional method of achieving dual-thickness gate oxides for FETs while forming a silicon oxide/silicon nitride/silicon oxide (ONO) layer on a substrate is depicted in the schematic cross-sectional views of FIGS. 1 and 2. In this approach a field oxide 12 is formed in and on the silicon substrate 10 to surround and electrically isolate the various device areas. The logic/analog device area (core area) is depicted in the left portion of FIG. 1, the I/o area is depicted in the center portion, and the SONOS area is depicted in the right portion of FIG. 1. For simplicity and purpose of discussion, the three device areas are depicted adjacent to each other; however, it should be understood that the device areas can be distributed differently on the substrate depending upon the circuit design.
In this conventional approach a blanket stacked layer is formed on the substrate. The stacked layer consists of a first silicon oxide (SiO2) layer 16, a silicon nitride (Si3N4) layer 18, and a top SiO2 layer 20, as shown in FIG. 1. As shown in FIG. 2, the stacked ONO layer is patterned to leave portions over the SONOS memory (cell) area. Then, as shown in FIG. 3, a first gate oxide 24 is grown over the core and I/O device areas and is patterned to leave the first gate oxide 24 over the I/O device areas, and a second gate oxide 28 is grown over the core area. Unfortunately, during processing to form the first and second gate oxides, the effects of cleaning and oxidizing can dramatically alter the thickness of the top SiO2 layer 20′.
Various methods of integrating SONOS or MONOS devices on a substrate have been reported in the literature. For example, U.S. Pat. No. 6,531,350 B2 to Satoh et al. describes a method for making twin MONOS devices on opposite sidewalls of a word line while simultaneously forming the memory gate and the logic gate. Nishizaka in U.S. Pat. No. 2004/0021171 A1 describes a method for making a non-volatile two-bit (node) device, with a node on each side of a polysilicon gate electrode. In U.S. Pat. No. 2004/0018685 A1 to Shibata, a method is described for making a non-volatile memory cell, with nodes adjacent to and on opposite sides of a polysilicon gate electrode. U.S. Pat. No. 2003/0155582 A1 to Mahajani et al. describes a method for making very thin gate oxides using a low-temperature in-situ steam generation process. The cited references do not address the problem of variations in the thickness of the top SiO2 on a SONOS device.
Therefore there is a need in the industry to provide a method that minimizes variations in the thickness of top SiO2 on SONOS devices when integrating SONOS devices with FETs having gate oxides of several different thicknesses on the same substrate.